Generally, in fabrication of an IC device, lithography processes may be utilized to print/pattern cavities, trenches, and/or recessed-areas for creating various components, elements, and circuits. A lithography process includes forming a layer of light or radiation-sensitive material, such as photoresist, above a layer of material or a substrate. The radiation-sensitive material is selectively exposed to a light generated by a light source (such as a deep ultraviolet or extreme ultraviolet source) to transfer a pattern defined by a mask to the radiation-sensitive material. The exposed layer of radiation-sensitive material is developed to define a patterned mask layer. Various process operations, such as etching or ion implantation processes, may then be performed on the underlying layer of material or substrate through the patterned mask layer.
With advancements in processes utilized to manufacture IC devices as well as industry demand for more efficient and smaller sized devices, physical dimensions of the patterns that are to be formed in the devices are reduced. In some instances, a single patterning lithography process may be incompatible for defining a compact layer, such as a metal layer in a memory cell, where multiple lithography steps (e.g., SADP) may need to be utilized for creating a single target pattern in a layer of material. For example, double patterning is an exposure method that involves splitting (i.e., dividing or separating) a dense overall target circuit pattern into two separate, simplified/less-dense patterns. The simplified patterns are then printed separately on a wafer utilizing two separate masks (where one of the masks is utilized to image one of the simplified patterns, and the other mask is utilized to image the other simplified pattern). However, with reduced device and layout geometries, the sizes of masks (e.g., block-mask) utilized in the process are also reduced; however, this may result in undesired effects on patterns produced through the masks.
FIG. 1A schematically illustrates an example layout diagram of a metal layer 100 for a SRAM cell where a 2-by-2 array of bitcells 101a, 101b, 101c, and 101d includes connectivity to various active regions. For example, the metal layer in bitcell 101a includes connectivity lines/segments 103a and 103b for a ground voltage (VSS); 105a and 105b for a positive voltage (VDD); 107a for a bitline-bar-0 (BLB0); 109a for a bitline-0 (BL0); and 111 for a wordline-2 (WL2). Geometry of a bitcell (e.g., 101a) includes contact-poly pitch (CPP) 113 and bitcell height 115 dimensions. In a SADP process utilized to pattern the layout of the metal layer 100, a side-to-side spacing 117 between two connecting parallel lines/segments, e.g., 103a and 111 or 109a and 111, may be determined by a thickness of a spacer (not shown) that was used in the process of creating the parallel lines/segments, whereas a tip-to-tip spacing 119, along the bitcell height dimension 115 may be determined by a width of a block-mask (not shown) that was also used in the process.
As shown in FIG. 1B, a block-mask pitch 121 between adjacent block-masks; e.g., 123a and 123b, is a function of the bitcell height 115; therefore, if the bitcell height 115 in a smaller SRAM is further reduced, a double patterning process may be necessary for the block-mask layer. Additionally, as the size of a block-mask is reduced, its geometry may become similar to a contact shape 125, as shown in FIG. 1C, which may be inefficient in cutting metal segments/lines. Still, even if a cut is made, the shape (e.g., sharply curved) of the tip edges 127 of the cut metal lines (e.g., 103a and 105a), as shown in FIG. 1D, may adversely impact the electrical functionality/characteristics (e.g., electrical field) of the segments. Moreover, a smaller block-mask utilized in fabrication of an IC device may reduce fabrication process margins and adversely impact manufacturing yield, time, cost, etc. of an IC device.
A need therefore exists for methodology enabling formation of metal routing in an IC device utilizing SADP with a block-mask without double patterning the block mask.